A High Speed Leakage Tolerant Domino Techniques

As the aspect ratio of the devices shrinks down, the power supply voltage should be reduced to meet low power requirements, and the threshold voltage should also be reduced to achieve high performance. This, however, leads to exponential increase in leakage current; hence the circuit’s reliability is also affected. A new domino circuit is proposed with reduced power and lower leakage for wide fan-in gates. The main goal was to make domino circuits more robust and with lower leakage and without dramatic speed degradation. The technique utilized in this paper is that, the pull-up network’s mirrored current is compared with its worst case leakage current and it decreases the upper and lower boundary of the voltage swing on the dynamic node. The parasitic capacitance on the dynamic node and the keeper size for very high fan-in gates is also reduced by the proposed circuit and hence the circuit can be used as a small keeper for wide fan-in gates to implement fast and robust circuits. The footer transistor is also used to reduce the leakage current. Simulation results of wide fan-in gates are designed using Tanner in 16-nm technology.